This invention relates to underfill encapsulant compounds prepared from epoxies to protect and reinforce the interconnections between an electronic component and a substrate in a microelectronic device. Microelectronic devices contain multiple types of electrical circuit components, mainly transistors assembled together in integrated circuit (IC) chips, but also resistors, capacitors, and other components. These electronic components are interconnected to form the circuits, and eventually are connected to and supported on a carrier or a substrate, such as a printed wire board. The integrated circuit component may comprise a single bare chip, a single encapsulated chip, or an encapsulated package of multiple chips. The single bare chip can be attached to a lead frame, which in turn is encapsulated and attached to the printed wire board, or it can be directly attached to the printed wire board. These chips are originally formed as a semiconductor wafer containing multiple chips. The semiconductor wafer is diced as desired into individual chips or chip packages.
Whether the component is a bare chip connected to a lead frame, or a package connected to a printed wire board or other substrate, the connections are made between electrical terminations on the electronic component and corresponding electrical terminations on the substrate. One method for making these connections uses polymeric or metallic material that is applied in bumps to the component or substrate terminals. The terminals are aligned and contacted together and the resulting assembly is heated to reflow the metallic or polymeric material and solidify the connection.
During its normal service life, the electronic assembly is subjected to cycles of widely varying temperature ranges. Due to the differences in the coefficient of thermal expansion for the electronic component, the interconnect material, and the substrate, this thermal cycling can stress the components of the assembly and cause it to fail. To prevent the failure, the gap between the component and the substrate is filled with a polymeric encapsulant, hereinafter called underfill or underfill encapsulant, to reinforce the interconnect material and to absorb some of the stress of the thermal cycling.
Two prominent uses for underfill technology are for reinforcing packages known in the industry as chip scale packages (CSP), in which a chip package is attached to a substrate, and flip-chip packages in which a chip is attached by an array of interconnections to a substrate.
In conventional capillary flow underfill applications, the underfill dispensing and curing takes place after the reflow of the metallic or polymeric interconnect. In this procedure, flux is initially applied on the metal pads on the substrate. Next, the chip is placed on the fluxed area of the substrate, on top of the soldering site. The assembly is then heated to allow for reflow of the solder joint. At this point, a measured amount of underfill encapsulant material is dispensed along one or more peripheral sides of the electronic assembly and capillary action within the component-to-substrate gap draws the material inward. After the gap is filled, additional underfill encapsulant may be dispensed along the complete assembly periphery to help reduce stress concentrations and prolong the fatigue life of the assembled structure. The underfill encapsulant is subsequently cured to reach its optimized final properties.
Recently, attempts have been made to streamline the process and increase efficiency by coating the underfill encapsulant directly on the semiconductor wafer before the wafer is diced into individual chips. The coating procedure, which can be performed via various methods, including screen printing, stencil printing and spin coating, allows for a single application of underfill to a single semiconductor wafer that is later diced into a large number of individual chips.
In order to be useful as a wafer level underfill encapsulant, the underfill must have several important properties. First, the material must be easy to apply uniformly on the wafer so that the entire wafer has a consistent coating. The underfill encapsulant that is applied to the wafer must not interfere with the clean dicing of the wafer into individual chips. The underfill encapsulant must be B-stageable, which means that the underfill must be solidified after its placement on a wafer to provide a smooth, non-tacky coating with minimal residual solvent.
If the starting underfill material is a solid, the solid is dispersed or dissolved in a solvent to form a paste and the paste applied to the wafer. The underfill is then heated to evaporate the solvent, leaving a solid, but uncured, underfill on the wafer. If the starting underfill material is a liquid or paste, the underfill is dispensed onto the wafer and heated to partially cure it to a solid state.
The B-stage process usually occurs at a temperature lower than about 150° C. without prematurely curing the underfill encapsulant. The final curing of the underfill encapsulant must be delayed until after the solder fluxing (in the situation that solder is the interconnect material) and interconnection, which occurs at a temperature of 183° C. in the case of tin/lead eutectic solder. The final curing of the underfill should occur rapidly after the solder bump flow and interconnection. During this final attachment of the individual chips to a substrate, the underfill encapsulant must flow in order to enable fillet formation, flux the solder bumps, and provide good adhesion between the chip, or chip passivation layer, the substrate, or the solder mask, and the solder joints. In particular instances, it can be useful to provide an unfilled liquid curable fluxing material directly on the substrate to faciliate interconnection.